Exsedia's IPalette toolset makes it easier and faster for VHDL and Verilog designers to build high-quality large scale systems. In a top-down approach where there are existing multiple HDL components, IPalette allows you to use block diagrams to structure and partition your design, then add in the internal descriptions using the IPalette code editor and Nimbus behavioral descriptions.

IPalette gives you structured VHDL or Verilog code-no more headaches tracing errors in connectivity between entity/architectures or modules.

IPalette also lets you build systems bottom-up by allowing you to take existing VHDL architecture or Verilog module code blocks and behavioral descriptions created in Nimbus, and bind them to block diagrams which define your system's hierarchy. By binding system-level modules from your components, you can then maximize design reuse.

Nimbus is a part of a tool set from Exsedia which assists the HDL (VHDL and/or Verilog) designer in constructing large-scale system designs.

Explore your algorithm: Leveraging algorithmic state machines (ASM) as a method of design entry, engineers can capture design intent at an early stage, thus reducing iteration and expediting design closure.

Validate your design: Using a highly intuitive ASM notation, design architectures are graphical so that you and your design team members can speed up analysis time and make better decisions in architectural trade-offs. And because is self-documenting, you can create "easily traceable" documentation, making design management and IP reuse a lot easier.

Verify and simulate: The power of Nimbus' verification feature lies in its design rule checking, which flags design rule violations such as racing conditions and conflict resolutions that may only become apparent during HDL simulation. The static and dynamic verification feature allows you to verify your design for syntax and semantic errors using animation. Nimbus has batch and interactive cycle-based simulation that allows you to generates testbench for subsequent RTL simulation, saving you time in testbench generation.

Generate code: The code generation engine employs intelligence techniques to produce clear, elegant, optimized Verilog and VHDL codes for industry standard synthesis. High-quality code generation means easier management.

Nimbus also provides an interactive and easy-to-use built-in cycle-based simulator for design verification. This tool even provides a built-in full function wave viewer to view the simulation results. After verification, the design can be translated to various vendor-specific RTL codes for synthesis or event-based simulations. Furthermore, to ensure consistent test-benches for the event based RTL simulators and the built-in cycle-based simulator, the test-benches used for verification within the Nimbus environment can be saved and translated to HDL format.